Method of forming self-aligned contacts

ABSTRACT

A method of forming self-aligned contacts that includes providing at least one stacked-gate structure on a semiconductor substrate, forming a first dielectric layer on the stacked-gate structure and the semiconductor substrate, forming a second dielectric layer on the first dielectric layer, the second dielectric layer being etch selective relative to the first dielectric layer, etching the second dielectric layer to expose a portion of the first dielectric layer formed on a top surface and along at least a portion of upper sidewalls of the stacked-gate structure, removing the exposed portion of the first dielectric layer, and forming a third dielectric layer on the sidewalls of the stacked-gate structure.

TECHNICAL FIELD

This invention pertains in general to a semiconductor integrated circuitand, more particularly, to a method of forming a self-aligned contact ina semiconductor integrated circuit.

BACKGROUND

A field-effect transistor (“FET”) generally includes an insulating layerformed on a semiconductor substrate, a polycrystalline silicon gateformed on the insulating layer, a pair of source/drain regions formed inthe semiconductor substrate, and a channel region formed below the gateinsulating layer and separated by the source/drain regions. In thefabrication of FETs, typical complementary metal-oxide-semiconductor(“CMOS”) techniques include a metallization process to electricallycouple source/drain pairs to circuits. The metallization process mayinclude providing a patterned mask layer over the semiconductorsubstrate to expose a source or drain region formed in the semiconductorsubstrate. Specifically, an opening is made through the patterned masklayer using conventional lithographic techniques for a later depositionof metal materials such as aluminum or aluminum alloys in the opening.In deep sub-micron CMOS processes, however, due to a higher devicedensity on a semiconductor substrate and a smaller device, integratedcircuit devices have been miniaturized. As a result, openings forforming metal contacts have smaller dimensions and become liable to maskmisalignment. To alleviate limitations set by mask alignment tolerances,self-aligned contact (“SAC”) techniques are generally used to allow fora less precise alignment of masks.

FIG. 1 shows a cross-sectional view of a conventional FET device 10.Referring to FIG. 1, FET device 10 formed on a semiconductor substrate12 includes a stacked-gate structure 14, a gate insulating layer 16formed on semiconductor substrate 12 and disposed under stacked-gatestructure 14, a source/drain pair 18 formed in semiconductor substrate12 and separated apart from each other by a channel region 20, andsidewall spacers 22 surrounding the sidewalls (not numbered) ofstacked-gate structure 14. Stacked-gate structure 14 may include aconductively doped polycrystalline silicon gate 24, a refractory metalgate 28, and an interlayer dielectric (“ILD”) 26 to isolate gates 24 and28. FET device 10 usually also includes a conformal layer 30 of siliconoxide formed over gate insulating layer 16 and stacked-gate structure 14to serve as a stress buffer layer.

A self-aligned contact (not shown) is then formed after source/drainpair 18 is ion implanted. Conventional methods of forming a self-alignedcontact may include providing a dielectric layer 32, for example, anoxide layer, over semiconductor substrate 12, and etching dielectriclayer 32, buffer layer 30 and gate insulating layer 16 to expose asource/drain region 18, thereby forming a contact opening 34 for a laterdeposition of contact metal (not shown). Since dielectric layer 32 andbuffer layer 30 are composed of silicon oxide, an etchant used to reducedielectric layer 32 would also attack buffer layer 30 formed betweenstacked-gate structure 14 and sidewall spacers 22, resulting in anexposure of metal layer 28 as circled, and causing a short-circuitbetween exposed metal layer 28 and the contact metal to be filled incontact opening 34.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a method that obviatesone or more of the problems due to limitations and disadvantages of therelated art.

Additional features and advantages of the present invention will be setforth in the description which follows, and in part will be apparentfrom the description, or may be learned by practice of the invention.The objectives and other advantages of the invention will be realizedand attained by the methods particularly pointed out in the writtendescription and claims thereof, as well as the appended drawings.

To achieve these and other advantages, and in accordance with thepurpose of the invention as embodied and broadly described, there isprovided a method of forming self-aligned contacts that includesproviding at least one stacked-gate structure on a semiconductorsubstrate, forming a first dielectric layer on the stacked-gatestructure and the semiconductor substrate, forming a second dielectriclayer on the first dielectric layer, the second dielectric layer beingetch selective relative to the first dielectric layer, etching thesecond dielectric layer to expose a portion of the first dielectriclayer formed on a top surface and along at least a portion of uppersidewalls of the stacked-gate structure, removing the exposed portion ofthe first dielectric layer, and forming a third dielectric layer on thesidewalls of the stacked-gate structure.

In one aspect, wherein the step of forming a first dielectric layercomprises oxidizing the stacked-gate structure and the semiconductorsubstrate.

In another aspect, further comprising forming a conformal firstdielectric layer.

Also in accordance with the present invention, there is provided amethod of forming self-aligned contacts that includes providing at leastone stacked-gate structure on a semiconductor substrate, oxidizing thestacked-gate structure and the semiconductor substrate to form a firstoxide layer, forming a sacrificial layer on the first oxide layer, thesacrificial layer being etch selective relative to the first oxidelayer, etching the sacrificial layer to expose the first oxide layerformed on a portion of a top surface and upper sidewalls of thestacked-gate structure, removing the first oxide layer unmasked by thesacrificial layer to expose the portion of the top surface and the uppersidewalls of the stacked-gate structure, forming a spacer along thesidewalls of the stacked-gate structure, forming a second oxide layer onthe spacer and the semiconductor substrate, the second oxide layer beingetch selective relative to the spacer, and etching the second oxidelayer and the first oxide layer to expose a contact region adjacent tothe stacked-gate structure.

In one aspect, wherein oxidizing the stacked-gate structure comprisesrapid thermal process with oxygen and hydrogen.

In another aspect, wherein oxidizing the stacked-gate structurecomprises in-situ stream generation process with oxygen and hydrogen.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory onlyand are not restrictive of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate embodiments consistent with theinvention and, together with the description, serve to explain theobjects, advantages, and principles of the invention.

In the drawings,

FIG. 1 shows a cross-sectional view of a conventional field-effecttransistor device; and

FIGS. 2 to 8 show a method of forming a self-aligned contact inaccordance with one embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to embodiments consistent with theinvention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers will be usedthroughout the drawings to refer to the same or like parts.

FIGS. 2 to 8 show a method of forming a self-aligned contact inaccordance with one embodiment of the present invention. Referring toFIG. 2, the method begins with providing a semiconductor substrate 50.Subsequently, a stacked-gate structure 52 is formed on semiconductorsubstrate 50. A source/drain pair and a channel may optionally be formedat this stage. Stacked-gate structure 52 includes a gate insulatinglayer 54, a first metal layer 56 formed on gate insulating layer 54, asecond metal layer 60, and an interlayer dielectric 58 formed betweenfirst metal layer 56 and second metal layer 60 to provide electricalisolation. In one embodiment, gate insulating layer 54 is composed ofsilicon oxide, first metal layer 56 includes a polycrystalline siliconlayer, and second metal layer 60 includes a refractory metal layer. Inanother embodiment, a third metal layer 62 comprised of tungsten siliconis formed on second metal layer 60 comprised of polycrystalline silicon.Third metal layer 62 may be used to enhance conductivity of stacked-gatestructure 52.

A passivation layer 64, for example, a silicon nitride layer, may beformed on top of third metal layer 62 to provide electrical insulation,protection of third metal layer 62 and planarization.

Referring to FIG. 3, subsequent to the formation of stacked-gatestructure 52, a continuous first dielectric layer 66 of a firstdielectric is formed on stacked-gate structure 52 and semiconductorsubstrate 50. First dielectric layer 66 may also be conformal. In oneembodiment, first dielectric layer 66 is comprised of silicon oxide, andmay be formed by oxidizing stacked-gate structure 52 and semiconductorsubstrate 50 through rapid thermal process (“RTP”) or in-situ streamgeneration (“ISSG”) process using oxygen and hydrogen. First dielectriclayer 66 may also be provided through deposition. First dielectric layer66 functions to serve as a buffer layer against stress generated duringsubsequent formation of sidewall spacers.

Referring to FIG. 4, a second dielectric layer 68 is formed on firstdielectric layer 66. Second dielectric layer 68 exhibits a high etchselectivity relative to first dielectric layer 66 to facilitate asubsequent etching treatment. In one embodiment, second dielectric layer68 includes silicon nitride, and first dielectric layer 66 includessilicon oxide. Second dielectric layer 68 is formed on first dielectriclayer 66 by a high-density chemical vapor deposition (“HDCVD”). Due tothe characteristics of HDCVD, second dielectric layer 68 formed alongupper sidewalls 70 of stacked-gate structure 52 is substantially thinnerthan that formed over semiconductor substrate 50 and on a top surface 72of stacked-gate structure 52. In one embodiment, second dielectric layer68 functions to serve as a sacrificial layer.

Referring to FIG. 5, second dielectric layer 68 is etched to exposefirst dielectric layer 66 formed on a portion of top surface 72 andalong upper sidewalls 70 of stacked-gate structure 52. In oneembodiment, H₃PO₄ is used to etch second dielectric layer 68.

Referring to FIG. 6, after etching second dielectric layer 68, exposedfirst dielectric layer 66 formed on a portion of top surface 72 andalong upper sidewalls 70 of stacked-gate structure 52 is removed by, forexample, a dip etch to expose portions of top surface 72 and uppersidewalls 70 of stacked-gate structure 52. Due to the fact that firstdielectric layer 66 exhibits a high etch selectivity relative to seconddielectric layer 68, the etching process only removes a small portion,if any, of first dielectric layer 66 masked by the remaining seconddielectric layer 68.

Referring to FIG. 7, subsequent to the removal of first dielectric layer66 unmasked by the remaining second dielectric layer 68, a thirddielectric layer 74 is formed along sidewalls 80 of stacked-gatestructure 52 to cover the remaining first dielectric layer 66 formed onsidewalls 80. In one embodiment, before forming third dielectric layer74, the remaining second dielectric layer 68 is completely removed. Inanother embodiment, second dielectric layer 68 and third dielectriclayer 74 are comprised of silicon nitride so that second dielectriclayer 68 may be retained during the formation of third dielectric layer74. Third dielectric layer 74 functions to serve as a spacer to surroundstacked-gate structure 52.

Referring to FIG. 8, subsequent to the formation of third dielectriclayer 74, a fourth dielectric layer 76 is formed over third dielectriclayer 74 and semiconductor substrate 50. Fourth dielectric layer 76exhibits a high etch selectivity relative to third dielectric layer 74to facilitate a subsequent etch treatment. In one embodiment, fourthdielectric layer 76 includes silicon oxide and third dielectric layer 74includes silicon nitride. Next, with a patterned defined photoresistlayer (not shown) provided over fourth dielectric layer 76, fourthdielectric layer 76 and remaining first dielectric layer 66 not coveredby the photoresist are etched to form at least one contact opening 78that exposes a contact region (not numbered) in semiconductor substrate50. The contact region may include a source or drain region of an FETdevice. The photoresist is then removed.

The present invention therefore also provides an integrated circuit thatincludes a stacked-gate structure formed on a semiconductor substrate,an oxide layer formed along lower sidewalls of the stacked-gatestructure, a spacer formed along and surrounding the sidewalls of thestacked-gate structure to cover the oxide layer, and a contact regionformed in the semiconductor substrate and disposed adjacent to thestacked-gate structure. The stacked-gate structure may include a firstmetal layer, a second metal layer, and a dielectric layer formed betweenthe first metal layer and the second metal layer. In one embodiment, thefirst metal layer includes polycrystalline silicon, and the second metallayer includes refractory metal such as tungsten silicon. In oneembodiment, the spacer includes silicon nitride and is etch selectiverelative to the oxide layer. Since the oxide layer is covered by thespacer, a loss of the oxide layer material, due to attack of etchantsduring formation of a self-aligned contact, and hence a short circuitcaused between a gate metal and a contact metal, may be avoided.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the disclosed processwithout departing from the scope or spirit of the invention. Otherembodiments of the invention will be apparent to those skilled in theart from consideration of the specification and practice of theinvention disclosed herein. It is intended that the specification andexamples be considered as exemplary only, with a true scope and spiritof the invention being indicated by the following claims.

1. A method of forming self-aligned contacts, comprising: providing atleast one stacked-gate structure on a semiconductor substrate; forming afirst dielectric layer on the stacked-gate structure and thesemiconductor substrate; forming a second dielectric layer on the firstdielectric layer, the second dielectric layer being etch selectiverelative to the first dielectric layer; etching the second dielectriclayer to expose a portion of the first dielectric layer formed on a topsurface and along at least a portion of upper sidewalls of thestacked-gate structure; removing the exposed portion of the firstdielectric layer; and forming a third dielectric layer on the sidewallsof the stacked-gate structure, wherein a first portion of the seconddielectric layer is substantially thinner along the upper sidewalls ofthe stacked-gate structure than a second portion of the seconddielectric layer formed over the semiconductor substrate.
 2. The methodof claim 1, further comprising forming a conformal first dielectriclayer.
 3. The method of claim 1, wherein the step of providing at leastone stacked-gate structure includes providing a gate insulating layer,providing a first metal layer over the gate insulating layer, providinga fourth dielectric layer over the first metal layer, and providing asecond metal layer over the fourth dielectric layer.
 4. The method ofclaim 1, further comprising forming a silicon oxide layer as the firstdielectric layer.
 5. The method of claim 1, further comprising forming asilicon nitride layer as the second dielectric layer.
 6. The method ofclaim 1, further comprising forming a silicon nitride layer as the thirddielectric layer.
 7. The method of claim 1, wherein the step of forminga first dielectric layer comprises oxidizing the stacked-gate structureand the semiconductor substrate.
 8. The method of claim 7, whereinoxidizing the stacked-gate structure comprises rapid thermal processwith oxygen and hydrogen.
 9. The method of claim 6, wherein oxidizingthe stacked-gate structure comprises in-situ stream generation processwith oxygen and hydrogen.
 10. The method of claim 1, further comprisingforming a fourth dielectric layer on the third dielectric layer and thesemiconductor substrate, the fourth dielectric layer being etchselective relative to the third dielectric layer.
 11. The method ofclaim 10, further comprising etching the fourth dielectric layer and thefirst dielectric layer to expose a contact region disposed adjacent tothe stacked-gate structure in the semiconductor substrate.
 12. Themethod of claim 10, further comprising forming a silicon oxide layer asthe fourth dielectric layer.
 13. The method of claim 1, furthercomprising forming the second dielectric layer by a high-densitychemical vapor deposition.
 14. The method of claim 1, further comprisingremoving the first dielectric layer using a dip etch.
 15. The method ofclaim 1, further comprising removing the second dielectric layer beforeforming a third dielectric layer along the sidewalls of the stacked-gatestructure.
 16. A method of forming self-aligned contacts, comprising:providing at least one stacked-gate structure on a semiconductorsubstrate; oxidizing the stacked-gate structure and the semiconductorsubstrate to form a first oxide layer; forming a sacrificial layer onthe first oxide layer, the sacrificial layer being etch selectiverelative to the first oxide layer; etching the sacrificial layer toexpose the first oxide layer formed on a portion of a top surface andupper sidewalls of the stacked-gate structure; removing the first oxidelayer unmasked by the sacrificial layer to expose the portion of the topsurface and the upper sidewalls of the stacked-gate structure; forming aspacer along the sidewalls of the stacked-gate structure; forming asecond oxide layer on the spacer and the semiconductor substrate, thesecond oxide layer being etch selective relative to the spacer; andetching the second oxide layer and the first oxide layer to expose acontact region adjacent to the stacked-gate structure.
 17. The method ofclaim 16, wherein the step of providing at least one stacked-gatestructure includes providing a gate insulating layer, providing a firstmetal layer over the gate insulating layer, providing a dielectric layerover the first metal layer, and providing a second metal layer over thedielectric layer.
 18. The method of claim 16, further comprising forminga silicon nitride layer as the sacrificial layer.
 19. The method ofclaim 16, wherein oxidizing the stacked-gate structure comprises rapidthermal process with oxygen and hydrogen.
 20. The method of claim 16,wherein oxidizing the stacked-gate structure comprises in-situ streamgeneration process with oxygen and hydrogen.